Solid-State Transformer Topology Selection: Two-Level vs Three-Level and DAB vs LLC

A solid-state transformer should not be treated as a conventional transformer rebuilt with semiconductor switches. That interpretation is too narrow and often leads to the wrong topology, component, and validation priorities.

For a basic voltage step-down and isolation function, a conventional line-frequency transformer remains difficult to replace. It is efficient, durable, relatively economical, and familiar to field personnel. The engineering value of a solid-state transformer becomes clearer when several functions must be combined within one controllable power-electronic interface.

These functions may include voltage transformation, galvanic isolation, AC/DC conversion, isolated DC/DC conversion, controlled power flow, accessible DC ports, and power-quality management. Once these requirements are considered together, topology selection becomes a system-level design decision rather than a comparison between individual converter circuits.

A practical development sequence is:

Topology selection → parameter design → engineering validation

These stages are interdependent. A topology that appears suitable during circuit analysis may become impractical after magnetic design, semiconductor stress calculation, light-load testing, insulation evaluation, thermal analysis, or fault-operation validation.

What Is a Solid-State Transformer?

ETH Zurich describes a solid-state transformer, or SST, as a galvanically isolated power-electronic interface between electrical systems. It uses controlled power conversion to combine voltage transformation and isolation with functions such as AC/DC conversion, DC/DC conversion, power-flow control, DC access, and grid-support capabilities. (pes-publications.ee.ethz.ch)

SST as an Integrated Power-Electronic Interface

The defining characteristic of an SST is not simply the use of switching devices. Its main value lies in integrating functions that would otherwise require several separate devices or conversion stages.

An SST may provide electrical isolation while controlling both the magnitude and direction of power transfer. It may create an intermediate DC link, provide a regulated DC output, interface with an AC load, or support power-quality functions at the grid connection.

This changes the basis of comparison.

A conventional transformer is primarily evaluated as a passive voltage-conversion and isolation device. An SST must be evaluated as a complete power-electronic system containing semiconductor switches, magnetic components, capacitors, gate drivers, control loops, protection functions, thermal paths, and an insulation structure.

Its suitability is therefore application-dependent. An SST is not automatically superior because it provides active control, and a conventional transformer is not obsolete simply because it lacks power-electronic functionality.

Why a Conventional Transformer Remains Strong for Basic Step-Down Applications

When the requirement is limited to dependable voltage transformation and galvanic isolation, a conventional line-frequency transformer still provides a strong engineering baseline.

The relevant question is not whether an SST outperforms a conventional transformer in every category. It is whether the application benefits enough from controllable conversion, DC access, power-flow management, and functional integration to justify the additional system complexity.

How an SST Architecture Divides Power-Conversion Tasks

                                              Three-Stage Solid-State Transformer Architecture

A common SST architecture separates the conversion process into three major stages:

1. A grid-side AC/DC stage

2. An isolated DC/DC stage

3. A load-side inverter or regulated DC output stage

This is not the only possible SST configuration. Modular, matrix-type, isolated-front-end, isolated-back-end, and multilevel architectures can organize these functions differently.

The three-stage model nevertheless provides a practical framework for understanding where the two major topology decisions normally occur:

• Two-level versus three-level conversion at the grid-facing stage

• DAB versus LLC conversion at the isolated DC/DC stage

Front-End AC/DC Conversion

The front-end stage connects the SST to the AC system and establishes a controlled DC link. Depending on the application, it may also manage controlled power flow and support the required power-quality functions.

The choice between a two-level and three-level structure affects:

• Semiconductor voltage stress

• Switching-node voltage steps

• Filter requirements

• Semiconductor count

• Gate-driver requirements

• Control complexity

• Protection sequencing

• System scalability

A lower semiconductor count is not always the most important objective. At a higher DC-link voltage, the blocking voltage placed on each device may become the dominant limitation.

A multilevel topology can distribute this voltage stress, but it introduces additional switching states, capacitors or clamping paths, and balancing requirements. The topology must therefore be evaluated as part of the complete converter rather than by device count alone.

Isolated DC/DC Conversion

The isolated DC/DC stage transfers power through a high- or medium-frequency transformer while maintaining galvanic isolation between electrical domains.

This stage cannot be selected independently of the transformer design. Leakage inductance, magnetizing inductance, resonant components, switching frequency, semiconductor capacitance, dead time, and modulation strategy all affect power transfer and soft-switching behavior.

DAB and LLC are both important candidates, but they use different power-transfer mechanisms. Their suitability depends on:

• Required power-flow direction

• Input-to-output voltage ratio

• Required gain range

• Expected load profile

• Soft-switching range

• Magnetic-component design

• Circulating-current limits

• Control capability

Two-Level vs Three-Level Converter Topologies for SST Front-End Stages

A two-level converter and a three-level converter should not be compared only by counting switches or comparing one peak-efficiency value.

A useful comparison begins with the operating requirements:

• What is the DC-link voltage?

• What blocking voltage must each semiconductor withstand?

• What switching-node voltage step is acceptable?

• What filtering is required?

• How much control complexity can the project support?

• Does the topology require neutral-point or capacitor-voltage balancing?

• Can abnormal switching states and fault conditions be validated?

How a Two-Level Converter Operates

A conventional two-level switching leg commutates its output node between the positive and negative DC-link rails.

The main switching devices must therefore withstand the relevant full DC-link voltage, including the margin needed for switching overshoot, transient events, protection response, and derating.

A two-level structure has fewer voltage states and generally fewer active and clamping devices than a three-level implementation. This can simplify:

• Gate driving

• Modulation

• Protection logic

• Shutdown sequencing

• PCB layout

• Fault analysis

The trade-off is that the switching node experiences the full DC-link voltage transition. This voltage step affects switching loss, electromagnetic stress, common-mode behavior, and the filtering required to control current ripple and emissions.

At higher DC-link voltages, device selection may become restrictive. A semiconductor with sufficient blocking voltage may not provide the desired balance between conduction loss, switching loss, switching speed, and thermal performance.

A two-level topology is therefore not inherently inferior. It remains attractive when device stress, filtering, switching frequency, insulation, and thermal requirements can be met without introducing unnecessary multilevel complexity.

How a Three-Level NPC Converter Distributes Voltage Stress

A three-level neutral-point-clamped converter uses a split DC link and clamping paths to create three switching-node voltage levels:

• (+V_{dc}/2)

• (0)

• (-V_{dc}/2)

Under the intended balanced condition, the voltage step applied to the output or filter can be reduced relative to a conventional two-level leg.

Individual devices may also operate at approximately half of the total DC-link blocking duty, depending on the switching state, protection strategy, voltage balance, and exact NPC implementation.

Reduced device-voltage stress may expand the available semiconductor options. The final device choice must still consider conduction loss, switching loss, transient margin, package behavior, and thermal constraints.

The voltage-stress advantage is accompanied by additional design requirements. An NPC leg contains more semiconductor devices and clamping paths, and its correct operation depends on safe switching sequences and stable split-bus voltages.

A 900 V DC link combined with 650 V devices is sometimes used to illustrate the voltage-stress benefit of multilevel conversion. However, topology identity matters.

Texas Instruments identifies TIDA-010957 as a three-level flying-capacitor converter, not an NPC converter. The design demonstrates the use of 650 V GaN devices with a DC-link voltage of up to 900 V, but it should not be presented as an NPC-specific reference design.

The general engineering principle remains valid: a multilevel converter can distribute voltage stress across its switching structure. The method differs among NPC, active NPC, T-type, Vienna, and flying-capacitor topologies.

                                        Two-Level vs Three-Level NPC Converter

Neutral-Point Voltage Balancing in a Three-Level NPC Topology

The midpoint of the split DC link is an active design constraint rather than a passive reference point.

Different switching states and current directions can charge and discharge the upper and lower DC-link capacitors unequally. If their voltages drift apart, the intended (+V_{dc}/2), (0), and (-V_{dc}/2) levels are no longer symmetrical.

This imbalance may affect:

• Semiconductor voltage stress

• Output waveform quality

• Modulation behavior

• Protection margin

• Available switching states

The controller may need to select redundant switching states or adjust the modulation sequence to influence neutral-point current.

Balancing capability can change with load direction, modulation index, power factor, and power-flow direction. Startup, shutdown, light-load operation, regeneration, and fault recovery also require verification.

Lower nominal device stress therefore does not make an NPC topology automatically easier to implement. The reduced switching-node voltage step is exchanged for additional state management and midpoint-control requirements.

                                                   NPC Neutral-Point Voltage Balancing

Two-Level vs Three-Level Selection Criteria

A two-level topology is generally attractive when simplicity, protection clarity, fault analysis, and control maturity dominate the project.

A three-level NPC topology becomes more attractive when DC-link voltage, device availability, waveform requirements, or switching performance make voltage-stress distribution valuable enough to justify the additional hardware and midpoint control.

DAB vs LLC for the Isolated DC/DC Stage

The isolated DC/DC topology must be selected according to the complete operating envelope rather than the topology name.

DAB and LLC both use high-frequency isolation, but their energy-transfer mechanisms and primary control variables are different. Their selection affects transformer design, current stress, voltage gain, soft-switching behavior, bidirectional operation, and light-load performance.

DAB Operating Principle and Engineering Decision Factors

A dual active bridge, or DAB, uses actively switched bridges on both sides of a high-frequency transformer.

Because both sides contain active switching bridges, the topology is naturally suited to controlled bidirectional power transfer.

Power is commonly regulated by changing the timing relationship between the bridge voltages. In a basic implementation, this is achieved through phase-shift control. More advanced modulation methods may introduce additional timing variables.

The transformer leakage inductance, or an additional series inductance, is part of the power-transfer mechanism. It shapes the current flowing between the bridges and contributes the stored energy needed during switching transitions.

This creates both flexibility and sensitivity.

The same inductance that enables controlled power transfer also affects:

• Current slope

• Peak current

• RMS current

• Reactive power

• Circulating energy

• Zero-voltage-switching range

A basic phase-shift strategy can be relatively direct, but it does not guarantee optimum performance across a wide voltage ratio and load range. Additional modulation variables can reduce current stress or extend the soft-switching region, but they also increase control and calibration complexity.

The principal DAB selection factors are:

• Whether bidirectional power flow is required

• The expected voltage ratio

• The required power range

• The acceptable circulating current

• The required soft-switching range

• The available control capability

• The transformer leakage-inductance target

• Startup, reversal, and fault-response requirements

LLC Operating Principle and Engineering Decision Factors

An LLC resonant converter is defined by three main resonant elements:

• Resonant inductance (L_r)

• Transformer magnetizing inductance (L_m)

• Resonant capacitance (C_r)

Part or all of the resonant inductance may be implemented through transformer leakage inductance. The magnetizing inductance belongs to the transformer magnetic structure, while the resonant capacitor is normally external.

Voltage gain is controlled mainly by changing the switching frequency relative to the resonant frequencies of the network.

The converter can provide favorable switching conditions when the resonant tank is designed around the intended:

• Input-voltage range

• Output voltage

• Load range

• Switching-frequency window

• Gain requirement

If the required conversion range becomes too wide, the LLC converter may need to operate far from its preferred resonant region. This can increase circulating current, expand the switching-frequency range, complicate magnetic design, or reduce the available soft-switching margin.

The statement that an LLC converter provides zero-voltage switching should therefore not be interpreted as unconditional.

The actual soft-switching boundary depends on:

• Load

• Resonant-tank parameters

• Magnetizing current

• Dead time

• Device capacitance

• Required voltage gain

• Switching frequency

A conventional LLC stage may also use passive rectification on the secondary side. That arrangement should not be assumed to provide the same bidirectional capability as a DAB containing active bridges on both sides.

                                              DAB vs LLC Isolated DC/DC Topologies

DAB vs LLC Selection Criteria

DAB is generally the more direct option when controlled bidirectional power transfer is a fundamental requirement.

LLC can be attractive when the operating range is clearly defined and the resonant tank can remain near favorable conditions for most of the duty cycle.

The decision should not be based on a single peak-efficiency result. A meaningful comparison requires equivalent voltage ratios, power levels, semiconductor technologies, magnetic constraints, cooling conditions, switching frequencies, and load points.

SST Design Must Coordinate Magnetics, Soft Switching, and Semiconductor Parameters

                                                     Coupled SST Design Parameters

Magnetic components, soft-switching conditions, and semiconductor parameters must not be calculated as separate work packages.

Each design area changes the operating conditions of the others.

A transformer optimized only for size may create excessive leakage or circulating current. A semiconductor selected only for low conduction loss may require switching conditions that the magnetic circuit cannot provide. A theoretically valid soft-switching condition may fail in the prototype because the real parasitic network differs from the model.

Why Magnetic Parameters Affect Switching Conditions

In a DAB, the transfer inductance affects:

• Transferred power

• Current slope

• Peak current

• RMS current

• Reactive energy

• Energy available for switching transitions

If the inductance is too small, current stress may rise rapidly. If it is too large, power-transfer capability or dynamic response may become restrictive.

The correct value depends on voltage ratio, switching frequency, modulation method, power level, and semiconductor behavior.

In an LLC converter, (L_r), (L_m), and (C_r) define the gain curve and resonant frequencies. They also influence circulating current, magnetizing current, switching-frequency range, and soft-switching boundaries.

A transformer modification intended to improve insulation or thermal performance may change its leakage and magnetizing inductances. This can move the converter away from its intended operating region.

Magnetic design must therefore consider more than core size and copper loss. It should also address:

• Functional leakage or resonant inductance

• Magnetizing inductance

• Parasitic capacitance

• Insulation distance

• Dielectric structure

• Winding arrangement

• Frequency-dependent winding loss

• Core loss

• Thermal path

• Partial-discharge behavior

Why Device Selection Cannot Be Separated from Layout and Thermal Design

A semiconductor datasheet does not represent the complete switching environment.

Device output capacitance affects the energy required for zero-voltage switching. Gate charge and internal gate resistance affect driver requirements. Package inductance and PCB interconnects influence overshoot, ringing, and switching speed.

Dead time must be coordinated with the current available to complete the switching transition. Gate resistance changes switching speed but also affects loss and overshoot.

The gate-driver supply, isolation barrier, protection response, and common-mode behavior must be compatible with the selected semiconductor technology.

Switching frequency then feeds back into magnetic size, semiconductor loss, cooling requirements, and insulation stress.

Increasing frequency may reduce magnetic volume, but it can also increase:

• Switching loss

• Winding loss

• Dielectric loss

• Thermal concentration

• Sensitivity to parasitic components

Electrical, magnetic, thermal, insulation, control, and layout decisions must therefore be solved as one coordinated design problem.

Five Engineering Validation Requirements for High-Voltage SST Projects

Five requirements deserve early attention in high-voltage and modular SST development:

1. Do not calculate magnetic components, soft switching, and semiconductor parameters independently.

2. Validate light-load operation separately.

3. Perform partial-discharge testing before full prototype assembly.

4. Keep gate-loop parasitic inductance below the specified project target.

5. Define the bypass strategy before building a multi-module system.

These requirements were associated with SST projects labeled ≥3 kV. The voltage label is incomplete unless the relevant voltage location and its AC or DC basis are defined.

                                        Five High-Voltage SST Engineering Validation Requirements

Validate Light-Load Operation Separately

Rated-load performance does not establish light-load performance.

In a DAB, zero-voltage switching depends partly on energy stored in the transfer inductance. At lower transferred power, the available current may be insufficient to charge and discharge the semiconductor capacitances during the switching interval.

The converter may therefore lose soft switching even when its rated-load waveform is satisfactory.

Auxiliary consumption also represents a larger share of input power at light load. Gate drivers, control electronics, sensing, cooling, and precharge circuits may dominate losses that are less significant at rated power.

An LLC stage can encounter a different limitation. Maintaining regulation at light load may require a large switching-frequency change or a dedicated light-load operating mode.

Light-load validation should examine:

• Switching-node waveforms

• Zero-voltage-switching margin

• RMS and circulating current

• Control-loop stability

• Auxiliary-power consumption

• Output regulation

• Thermal distribution

No fixed load percentage should be treated as a universal definition of light load. Test points should reflect the actual application duty cycle.

Perform Partial-Discharge Testing Before Full Prototype Assembly

Partial-discharge risk should be evaluated before the insulation structure is locked into the complete mechanical assembly.

Early testing can reveal weaknesses in:

• Transformer windings

• Interlayer insulation

• Potting materials

• Terminals

• Bus structures

• Connectors

• Electric-field concentration regions

Finding these problems before final assembly makes it easier to locate the defect and revise the insulation geometry.

IEC 60270:2025 defines the general charge-based framework for partial-discharge terminology, quantities, measurement frequencies, test circuits, calibration, measuring methods, and interference handling. It applies to charge-based partial-discharge measurements in electrical apparatus, components, and systems under specified AC or DC test conditions. (IEC Webstore)

IEC 60270 does not establish one universal SST acceptance limit, nor does it specify that all testing must occur before prototype assembly.

The required test voltage, partial-discharge inception voltage, extinction voltage, apparent-charge limit, duration, and acceptance criteria must be determined from the applicable equipment requirements, insulation coordination, product standard, or customer specification.

Early partial-discharge testing is an engineering sequencing measure, not a replacement for final system qualification.

Keep Gate-Loop Parasitic Inductance Below 10 nH

For the high-speed switching design considered here, gate-loop parasitic inductance must remain below 10 nH.

This target should be treated as a project-specific limit rather than a universal SST rule. The appropriate value depends on:

• Semiconductor technology

• Device package

• Driver placement

• Switching speed

• Gate resistance

• Kelvin-source implementation

• Measurement or extraction boundary

Gate-loop inductance affects turn-on and turn-off behavior. Excessive inductance may contribute to:

• Gate-voltage overshoot

• Gate-voltage undershoot

• Oscillation

• Delayed switching

• Parasitic turn-on

• Increased switching loss

• Device overstress

• Reduced protection effectiveness

The gate driver should be placed close to the semiconductor device. The path from the driver output to the gate and back to the driver return should be short and compact.

Where available, a Kelvin-source or Kelvin-emitter connection should separate the gate-drive return from the main power-current path.

The final inductance must be verified in the actual layout rather than inferred from the schematic alone.

Define a Bypass Strategy Before Building a Modular SST

Modularity does not automatically provide fault tolerance.

A multi-cell SST can continue operating after a module fault only when the architecture has been designed for that condition.

The system may require:

• Redundant voltage capability

• A physical bypass path

• Fault detection

• Fault isolation

• Control reconfiguration

• Voltage redistribution

• A defined degraded operating mode

These functions must be treated separately.

Fault detection identifies an abnormal module.
Fault isolation prevents the fault from propagating.
Physical bypass creates an alternative current path.
Control reconfiguration changes the commands applied to the remaining modules.
Voltage redistribution prevents healthy modules from being overstressed.
Degraded operation defines the remaining permissible power level.

A bypass switch without sufficient voltage margin in the remaining modules does not create a fault-tolerant system.

Similarly, redundant modules without validated detection, isolation, and control sequences may not improve practical system availability.

The bypass strategy should therefore be established before the module rating, insulation structure, control hierarchy, and protection hardware are finalized.

Define the Meaning of the ≥3 kV Boundary

The phrase “applicable to ≥3 kV SST projects” is incomplete unless the referenced voltage is identified.

It may refer to:

• AC input line-to-line voltage

• AC line-to-ground voltage

• DC-link voltage

• Output voltage

• Individual module voltage

• Insulation test voltage

• Complete system rating

These values are not interchangeable.

A 3 kV DC link and a 3 kV AC system do not create identical semiconductor, insulation, grounding, or test requirements.

A cascaded architecture may also divide the system voltage among several modules, making the module-level electrical stress very different from the terminal voltage.

The five engineering requirements remain relevant, but the ≥3 kV label should not be converted into a formal voltage classification or mandatory test threshold until its electrical reference is defined.

A Practical SST Topology Selection Workflow

SST development should be treated as an iterative process.

The initial topology defines the design space, but parameter calculations and validation results may require the topology or operating range to be revised.

Step 1: Define System Functions Before Selecting a Topology

The first task is to determine what the SST must accomplish.

The requirements should define:

• Input and output voltage domains

• AC and DC interfaces

• Galvanic-isolation requirements

• Power-flow direction

• Continuous and peak power

• Expected load profile

• Required DC ports

• Power-quality functions

• Redundancy and fault-operation requirements

• Cooling and installation constraints

• Insulation and partial-discharge requirements

• Maintenance capability

Only after these functions are clear should the converter topology be selected.

A system requiring controlled reverse power flow should not be evaluated in the same way as a unidirectional regulated supply. A modular medium-voltage interface also requires a different decision process from a single low-voltage converter.

Step 2: Design Electrical, Magnetic, Thermal, and Control Parameters Together

The selected topology establishes relationships among semiconductor stress, switching frequency, transformer parameters, resonant or transfer inductance, control variables, and thermal limits.

Parameter design should follow a coordinated loop:

1. Define the electrical stress and operating range.

2. Select candidate semiconductor technologies and voltage classes.

3. Establish possible switching frequencies and modulation methods.

4. Design the transformer and functional inductance.

5. Recalculate current stress and soft-switching boundaries.

6. Estimate semiconductor and magnetic losses.

7. Check thermal feasibility.

8. Review insulation and layout constraints.

9. Repeat until the electrical and physical designs are consistent.

The final result should describe an operating map rather than one rated operating point.

Step 3: Validate Load Range, Insulation, Switching Loops, and Fault Operation

Engineering validation must cover more than nominal power and peak efficiency.

The test program should include:

• Rated and off-nominal voltage conditions

• Full-load operation

• Light-load operation

• Power-flow reversal where applicable

• Startup and shutdown

• Insulation behavior

• Switching-loop dynamics

• Thermal limits

• Modular bypass operation

A successful rated-load test proves only that one operating condition has been achieved.

If validation reveals inadequate soft-switching margin, excessive current stress, midpoint drift, insulation weakness, thermal concentration, or fault-recovery problems, the design must return to the parameter or topology stage.

                                                 Iterative SST Development Workflow

Common SST Topology Selection Mistakes

Treating an SST as an Electronic Version of a Conventional Transformer

This approach ignores the main reason to use an SST: the integration of controlled conversion, isolation, DC access, and power-quality functions.

When only passive voltage step-down and isolation are required, a conventional transformer may remain the stronger engineering solution.

Choosing a Three-Level Topology Without Planning Neutral-Point Control

Lower nominal semiconductor stress does not eliminate system complexity.

An NPC design must manage split-bus voltage, redundant switching states, startup, shutdown, abnormal conditions, and protection sequencing.

Neutral-point behavior should be included in the control and validation specification from the beginning.

Selecting DAB or LLC from a Single Efficiency Number

Efficiency data are meaningful only when the operating conditions are comparable.

Voltage ratio, power level, semiconductor technology, transformer design, modulation, switching frequency, cooling, and load point can all change the result.

A peak-efficiency value does not describe the complete operating envelope.

Assuming Rated-Load Testing Completes the Validation Process

Light-load switching, insulation behavior, gate-loop dynamics, thermal distribution, and modular fault handling can fail even when rated-load power conversion appears normal.

The validation plan must reflect the real operating conditions and credible fault states of the system.

Conclusion: Select the SST Architecture as a Complete System

A solid-state transformer becomes valuable when an application requires more than passive voltage transformation.

Its engineering case is based on integrating isolation, AC/DC conversion, DC/DC conversion, controlled power flow, DC ports, and power-quality functions.

That integration also makes topology selection more demanding.

A two-level front end may provide the most direct solution when semiconductor stress and filtering remain manageable.

A three-level NPC structure may improve voltage-stress distribution and reduce switching-node voltage steps, but it introduces additional devices, switching states, and neutral-point-control requirements.

A DAB isolated stage is well suited to controlled bidirectional power transfer, but its current stress and soft-switching range depend on inductance, voltage ratio, load, and modulation.

An LLC stage can provide favorable resonant operation within a defined gain range, but its frequency range and soft-switching behavior must be validated across the actual duty cycle.

A topology decision is incomplete until the magnetic design, semiconductor stress map, thermal limits, insulation structure, control envelope, light-load behavior, and fault-operation strategy have been verified together.

Frequently Asked Questions

What is the main difference between a solid-state transformer and a conventional transformer?

A conventional transformer primarily provides passive voltage transformation and galvanic isolation.

An SST combines isolation with actively controlled AC/DC and DC/DC conversion, power-flow control, DC access, and potentially power-quality functions. The SST provides broader system functionality, while the conventional transformer remains highly competitive for simple and reliable voltage transformation.

When should an SST use a two-level or three-level converter topology?

A two-level topology is suitable when the DC-link voltage, device ratings, switching performance, and filtering requirements can be managed without additional multilevel complexity.

A three-level topology becomes attractive when distributing semiconductor voltage stress or reducing switching-node voltage steps provides enough benefit to justify additional devices, switching states, and voltage-balancing requirements.

Why is neutral-point voltage balancing important in a three-level NPC converter?

An NPC converter uses a split DC link to create (+V_{dc}/2), (0), and (-V_{dc}/2) switching levels.

Unequal charging of the upper and lower DC-link capacitors can shift the midpoint voltage, distort the intended switching levels, and change semiconductor stress. Loading, modulation, startup, shutdown, and power-flow direction can all influence the balance.

Is DAB or LLC better for the isolated DC/DC stage of an SST?

Neither topology is universally better.

DAB is generally more direct when active bidirectional power flow is essential. LLC can be attractive when the gain range is well controlled and the resonant tank can remain near favorable operating conditions.

The selection should consider voltage ratio, load range, soft-switching boundaries, circulating current, magnetic design, and control complexity.

Why must SST light-load performance be tested separately?

Soft-switching conditions and regulation behavior can change significantly at low power.

A DAB may no longer have sufficient inductive energy to maintain zero-voltage switching. An LLC may require a larger switching-frequency change or a dedicated light-load mode.

Auxiliary consumption also becomes a larger share of total loss, so rated-load results cannot predict light-load efficiency or stability.

What should be validated before assembling a high-voltage SST prototype?

The design team should validate the coupled magnetic, soft-switching, and semiconductor parameters; light-load behavior; insulation and partial-discharge performance; gate-loop layout; thermal distribution; and fault-operation strategy.

In a modular system, bypass operation and control reconfiguration should be defined before module ratings and protection hardware are finalized.